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1 ? fn8130.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005-2006. all rights reserved all other trademarks mentioned are the property of their respective owners. x5168, x5169 (replaces x25268, x25169) cpu supervisor with 16kbit spi eeprom these devices combine three popular functions, power-on reset control, supply voltage supervision, and block lock protect serial eeprom memory in one package. this combination lowers system cost, reduces board space requirements, and increases reliability. applying power to the device activates the power-on reset circuit which holds reset /reset active for a period of time. this allows the power supply and oscillator to stabilize before the processor can execute code. the device?s low v cc detection circuitry protects the user?s system from low voltage conditions by holding reset /reset active when v cc falls below a minimum v cc trip point. reset /reset remains a sserted until v cc returns to proper operating level and stabilizes. five industry standard v trip thresholds are available, however, intersil?s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold in applications requiring higher precision. features ?low v cc detection and reset assertion - five standard reset threshold voltages - re-program low v cc reset threshold voltage using special programming sequence - reset signal valid to v cc = 1v ? long battery life with low power consumption - <50a max standby current, watchdog on - <1a max standby current, watchdog off - <400a max active current during read ? 16kbits of eeprom ? built-in inadvertent write protection - power-up/power-down protection circuitry - protect 0, 1/4, 1/2 or al l of eeprom array with block lock ? protection - in circuit programmable rom mode ? 2mhz spi interface modes (0,0 & 1,1) ? minimize eeprom programming time - 32-byte page write mode - self-timed write cycle - 5ms write cycle time (typical) ? 2.7v to 5.5v and 4.5v to 5.5v power supply operation ? available packages - 14 ld tssop, 8 ld soic, 8 ld pdip ? pb-free plus anneal available (rohs compliant) block diagram data register command decode & control logic si so sck cs v cc reset timebase power-on and generation v trip + - reset /reset reset low voltage status register protect logic 4kbits 4kbits 8kbits eeprom array wp x5168 = reset x5169 = reset data sheet june 15, 2006
2 fn8130.2 june 15, 2006 ordering information part number reset (active low) part marking part number reset (active high) part marking v cc range (v) v trip range (v) temp range (c) package pkg. dwg # x5168p-4.5a x5168p al x5169p-4.5a x5169p al 4.5-5.5 4.5-4.75 0 to 70 8 ld pdip mdp0031 x5168pz-4.5a (note) x5168p z al x5169pz-4.5a (note) x5169p z al 0 to 70 8 ld pdip** (pb-free) mdp0031 x5168pi-4.5a x5168p am x5169pi-4.5a x5169p am -40 to 85 8 ld pdip mdp0031 x5168piz-4.5a (note) x5168p z am x5169piz-4.5a (note) x5169p z am -40 to 85 8 ld pdip** (pb-free) mdp0031 x5168s8-4.5a x5168 al x5169s8-4.5a x5169 al 0 to 70 8 ld soic mdp0027 x5168s8z-4.5a (note) x5168 z al x5169s8z-4.5a (note) x5169 z al 0 to 70 8 ld soic (pb-free) mdp0027 x5168s8i-4.5a* x5168 am x5169s8i-4.5a x5169 am -40 to 85 8 ld soic mdp0027 x5168s8iz-4.5a* (note) x5168 z am x5169s8iz-4.5a (note) x5169 z am -40 to 85 8 ld soic (pb-free) mdp0027 x5168v14-4.5a x5168v al x5169v14-4.5a x5169v al 0 to 70 14 ld tssop m14.173 x5168v14z-4.5a (note) x5168v z al x5169v14z-4.5a (note) x5169v z al 0 to 70 14 ld tssop (pb-free) m14.173 x5168v14i-4.5a x5168v am x5169v14i-4.5a x5169v am -40 to 85 14 ld tssop m14.173 x5168v14iz-4.5a (note) x5168v z am x5169v14iz-4.5a (note) x5169v z am -40 to 85 14 ld tssop (pb-free) m14.173 x5168p x5168p x5169p x5169p 4.5-5.5 4.25-4.5 0 to 70 8 ld pdip mdp0031 x5168pz (note) x5168p z x5169pz (note) x5169p z 0 to 70 8 ld pdip** (pb-free) mdp0031 x5168pi x5168p i x5169pi x5169p i -40 to 85 8 ld pdip mdp0031 x5168piz (note) x5168p z i x5169piz (note) x5169p z i -40 to 85 8 ld pdip** (pb-free) mdp0031 x5168s8* x5168 x5169s8* x5169 0 to 70 8 ld soic mdp0027 x5168s8z* (note) x5168 z x5169s8z* (note) x5169 z 0 to 70 8 ld soic (pb-free) mdp0027 x5168s8i* x5168 i x5169s8i* x5169 i -40 to 85 8 ld soic mdp0027 x5168s8iz* (note) x5168 z i x5169s8iz* (note) x5169 z i -40 to 85 8 ld soic (pb-free) mdp0027 x5168v14* x5168v x5169v14* x5169v 0 to 70 14 ld tssop m14.173 x5168v14z* (note) x5168v z x5169v14z* (note) x5169v z 0 to 70 14 ld tssop (pb-free) m14.173 x5168v14i* x5168v i x5169v14i* x5169v i -40 to 85 14 ld tssop m14.173 x5168v14iz* (note) x5168v z i x5169v14iz* (note) x5169v z i -40 to 85 14 ld tssop (pb-free) m14.173 x5168p-2.7a x5168p an x5169p-2.7a x5169p an 2.7-5.5 2.85-3.0 0 to 70 8 ld pdip mdp0031 x5168pz-2.7a (note) x5168p z an x5169pz-2.7a (note) x5169p z an 0 to 70 8 ld pdip** (pb-free) mdp0031 x5168pi-2.7a x5168p ap x5169pi-2.7a x5169p ap -40 to 85 8 ld pdip mdp0031 x5168piz-2.7a (note) x5168p z ap x5169piz-2.7a (note) x5169p z ap -40 to 85 8 ld pdip** (pb-free) mdp0031 x5168s8-2.7a* x5168 an x5169s8-2.7a x5169 an 0 to 70 8 ld soic mdp0027 x5168s8z-2.7a* (note) x5168 z an x5169s8z-2.7a (note) x5169 z an 0 to 70 8 ld soic (pb-free) mdp0027 x5168s8i-2.7a* x5168 ap x5169s8i-2.7a x5169 ap -40 to 85 8 ld soic mdp0027 x5168s8iz-2.7a (note) x5168 z ap x5169s8iz-2.7a (note) x5169 z ap -40 to 85 8 ld soic (pb-free) mdp0027 x5168, x5169
3 fn8130.2 june 15, 2006 pin configuration x5168v14-2.7a x5168v an x5169v14-2.7a x5168v an 2.7-5.5 2.85-3.0 0 to 70 14 ld tssop m14.173 x5168v14z-2.7a (note) x5168v z an x5169v14z-2.7a (note) x5169v z an 0 to 70 14 ld tssop (pb-free) m14.173 x5168v14i-2.7a x5168v ap x5169v14i-2.7a x5169v ap -40 to 85 14 ld tssop m14.173 x5168v14iz-2.7a (note) x5168v z ap x5169v14iz-2.7a (note) x5169v z ap -40 to 85 14 ld tssop (pb-free) m14.173 x5168p-2.7 x5168p f x5169p-2.7 x5169p f 2.7-5.5 2.55-2.7 0 to 70 8 ld pdip mdp0031 x5168pz-2.7 (note) x5168p z f x5169pz-2.7 (note) x5169p z f 8 ld pdip** (pb-free) mdp0031 x5168pi-2.7 x5168p g x5169pi-2.7 x5169p g -40 to 85 8 ld pdip mdp0031 x5168piz-2.7 (note) x5168p z g x5169piz-2.7 (note) x5169p z g 8 ld pdip** (pb-free) mdp0031 x5168s8-2.7* x5168 f x5169s8-2.7* x5169 f 0 to 70 8 ld soic mdp0027 x5168s8z-2.7* (note) x5168 z f x5169s8z-2.7* (note) x5169 z f 8 ld soic (pb-free) mdp0027 x5168s8i-2.7* x5168 g x5169s8i-2.7* x5169 g -40 to 85 8 ld soic mdp0027 x5168s8iz-2.7* (note) x5168 z g x5169s8iz-2.7* (note) x5169 z g 8 ld soic (pb-free) mdp0027 x5168v14-2.7* x5168v f x5169v14-2.7* x5169v f 0 to 70 14 ld tssop m14.173 x5168v14z-2.7* (note) x5168v z f x5169v14z-2.7* (note) x5169v z f 0 to 70 14 ld tssop (pb-free) m14.173 x5168v14i-2.7* x5168v g x5169v14i-2.7* x5168v g -40 to 85 14 ld tssop m14.173 x5168v14iz-2.7* (note) x5168v z g x5169v14iz-2.7* (note) x5168v z g -40 to 85 14 ld tssop (pb-free) m14.173 note: intersil pb-free plus anneal products em ploy special pb-free material sets; molding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb- free products are msl classified at pb-free peak reflow tem peratures that meet or exceed the pb-free requirements of ipc/jedec j std-020. *add "-t1" suffix for tape and reel. **pb-free pdips can be used for through hole wave solder processi ng only. they are not intended for use in reflow solder proces sing applications. ordering information (continued) part number reset (active low) part marking part number reset (active high) part marking v cc range (v) v trip range (v) temp range (c) package pkg. dwg # 8 ld soic/pdip cs wp so 1 2 3 4 reset /reset 8 7 6 5 v cc 14 ld tssop so wp v ss 1 2 3 4 5 6 7 reset /reset sck si 14 13 12 11 10 9 8 nc v cc nc x5168/x5169 v ss sck si cs nc nc nc nc x5168/x5169 x5168, x5169
4 fn8130.2 june 15, 2006 pin description pin (soic/pdip) pin tssop name function 11cs chip select input. cs high, deselects the device and the so output pin is at a high impedance state. unless a nonvol atile write cycle is under way, the device will be in the standby power mode. cs low enables the device, placing it in the active power mode. prior to the start of any operation after powe r-up, a high to low transition on cs is required. 22so serial output. so is a push/pull serial data output pin. a read cycle shif ts data out on this pin. the falling edge of the serial cl ock (sck) clocks the data out. 58si serial input. si is a serial data input pin. input all opcodes, byte addresses, and memory data on this pin. the rising edge of the serial clock (sck) latches the input data. send all opcodes (table 1), addresses and data msb first. 69sck serial clock. the serial clock controls the serial bus timing for data input and output. the rising edge of sck latches in the opcode, address, or data bits present on the si pin. the falling edge of sck changes the data output on the so pin. 36wp write protect. the wp pin works in conjunction with a nonvol atile wpen bit to ?lock? the setting of the watchdog timer control and the memory write protect bits. 47v ss ground 814v cc supply voltage 7 13 reset / reset reset output . reset /reset is an active low/high, open drain output which goes active whenever v cc falls below the minimum v cc sense level. it will remain active until v cc rises above the minimum v cc sense level for 200ms. reset /reset goes active if the watchdog timer is enabled and cs remains either high or low longer than the selectable watchdog time out period. a falling edge of cs will reset the watchdog timer. reset /reset goes active on power- up at about 1v and remains active for 200ms after the power supply stabilizes. 3-5,10-12 nc no internal connections x5168, x5169
5 fn8130.2 june 15, 2006 principles of operation power-on reset application of power to the x5168, x5169 activates a power- on reset circuit. this circuit goes active at about 1v and pulls the reset /reset pin active. this signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. when v cc exceeds the device v trip value for 200ms (nominal) the circuit releases reset /reset, allowing the processor to begin executing code. low voltage monitoring during operation, the x5168, x5169 monitors the v cc level and asserts reset /reset if supply vo ltage falls below a preset minimum v trip . the reset /reset signal prevents the microprocessor from operating in a power fail or brownout condition. the reset /reset signal remains active until the voltage drops below 1v. it also remains active until v cc returns and exceeds v trip for 200ms. v cc threshold reset procedure the x5168, x5169 has a standard v cc threshold (v trip ) voltage. this value will not change over normal operating and storage conditions. however, in applications where the standard v trip is not exactly right, or for higher precision in the v trip value, the x5168, x5169 threshold may be adjusted. setting the v trip voltage this procedure sets the v trip to a higher voltage value. for example, if the current v trip is 4.4v and the new v trip is 4.6v, this procedure directly makes the change. if the new setting is lower than the current setting, then it is necessary to reset the trip point before setting the new value. to set the new v trip voltage, apply the desired v trip threshold to the v cc pin and tie the cs pin and the wp pin high. reset /reset and so pins are left unconnected. then apply the programming voltage v p to both sck and si and pulse cs low then high. remove v p and the sequence is complete. resetting the v trip voltage this procedure sets the v trip to a ?native? voltage level. for example, if the current v trip is 4.4v and the v trip is reset, the new v trip is something less than 1.7v. this procedure must be used to set the voltage to a lower value. to reset the v trip voltage, apply a voltage between 2.7 and 5.5v to the v cc pin. tie the cs pin, the wp pin, and the sck pin high. reset /reset and so pins are left unconnected. then apply the programming voltage v p to the si pin only and pulse cs low then high. remove v p and the sequence is complete. sck si v p v p cs figure 1. set v trip voltage sck si v cc v p cs figure 2. reset v trip voltage x5168, x5169
6 fn8130.2 june 15, 2006 v trip programming apply 5v to v cc decrement v cc reset pin goes active? measured v trip - desired v trip done execute sequence reset v trip set v cc = v cc applied = desired v trip execute sequence set v trip new v cc applied = old v cc applied + error (v cc = v cc - 10mv) execute sequence reset v trip new v cc applied = old v cc applied - error error emax error = 0 yes no error > emax emax = maximum desired error figure 3. v trip programming sequence flow chart x5168/ 1 2 3 4 8 7 6 5 v trip adj. program nc nc v p reset v trip test v trip set v trip nc reset 4.7k 4.7k 10k 10k + figure 4. sample v trip reset circuit x5169 x5168, x5169
7 fn8130.2 june 15, 2006 spi serial memory the memory portion of the device is a cmos serial eeprom array with intersil?s block lock protection. the array is internally organized as x 8. the device features a serial peripheral interface (spi) and software protocol allowing operation on a simple four-wire bus. the device utilizes intersil?s proprietary direct write ? cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. the device is designed to interface directly with the synchronous serial peripheral interface (spi) of many popular microcontroller families. it contains an 8-bit instruction register that is accessed via the si input, with data being clocked in on the rising edge of sck. cs must be low during the entire operation. all instructions (table 1), addresses and data are transferred msb first. data input on the si line is latched on the first rising edge of sck after cs goes low. data is output on the so line by the falling edge of sck. sck is static, allowing the user to stop the clock and then start it again to resume operations where left off. write enable latch the device contains a write enable latch. this latch must be set before a write operation is initiated. the wren instruction will set the latch and the wrdi instruction will reset the latch (figure 3). this latch is automatically reset upon a power-up condition and after the completion of a valid write cycle. status register the rdsr instruction provides a ccess to the status register. the status register may be read at any time, even during a write cycle. the status regist er is formatted as follows: the write-in-progress (wip) bit is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. the wip bit is read using the rdsr instruction. when set to a ?1?, a nonvolatile write operation is in progress. when set to a ?0?, no write is in progress. note: *instructions are shown msb in leftmost pos ition. instructions are transferred msb first. 7 65 43210 wpen flb 0 0 bl1 bl0 wel wip table 1. instruction set instruction name instruction format* operation wren 0000 0110 set the write enable latch (enable write operations) sflb 0000 0000 set flag bit wrdi/rflb 0000 0100 reset the write enable latch/reset flag bit rdsr 0000 0101 read status register wrsr 0000 0001 write status register (wat chdog, block lock, wpen and flag bits) read 0000 0011 read data from memory array beginning at selected address write 0000 0010 write data to memory array beginning at selected address table 2. block protect matrix wren cmd status register device pin block block status register wel wpen wp# protected block unprotected block wpen, bl0, bl1 wd0, wd1 0 x x protected protected protected 1 1 0 protected writable protected 1 0 x protected writable writable 1 x 1 protected writable writable x5168, x5169
8 fn8130.2 june 15, 2006 the write enable latch (wel) bit indicates the status of the write enable latch. when wel = 1, the latch is set high and when wel = 0 the latch is reset low. the wel bit is a volatile, read only bit. it can be set by the wren instruction and can be reset by the wrds instruction. the block lock bits, bl0 and bl1, set the level of block lock protection. these nonvolatile bits are programmed using the wrsr instruction and allow the user to protect one quarter, one half, all or none of the eeprom array. any portion of the array that is block lock protected can be read but not written. it will remain protected until the bl bits are altered to disable block lock protection of that portion of memory. the flag bit shows the status of a volatile latch that can be set and reset by the system using the sflb and rflb instructions. the flag bit is automatically reset upon power-up. the nonvolatile wpen bit is programmed using the wrsr instruction. this bit works in conjunction with the wp pin to provide an in-circuit programmable rom function (table 2). wp is low and wpen bit programmed high disables all status register write operations. in circuit programmable rom mode this mechanism protects the block lock and watchdog bits from inadvertent corruption. in the locked state (programmable rom mode) the wp pin is low and the nonvolatile bit wpen is ?1?. this mode disables nonvolatile writes to the device?s status register. setting the wp pin low while wpen is a ?1? while an internal write cycle to the status register is in progress will not stop this write operation, but the operation disables subsequent write attempts to the status register. when wp is high, all functions, including nonvolatile writes to the status register operate normally. setting the wpen bit in the status register to ?0? blocks the wp pin function, allowing writes to the status register when wp is high or low. setting the wpen bit to ?1? while the wp pin is low activates the programmable rom mode, thus requiring a change in the wp pin prior to subsequent status register changes. this allows manufacturing to install the device in a system with wp pin grounded and still be able to program the status register. manufacturing can then load configuration data, manufacturi ng time and other parameters into the eeprom, then set the portion of memory to be protected by setting the block lock bits, and finally set the ?otp mode? by setting the wpen bit. data changes now require a hardware change. status register bits array addresses protected bl1 bl0 x5168/x5169 0 0 none 0 1 $0600-$07ff 1 0 $0400-$07ff 1 1 $0000-$07ff 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 7 654321 0 data out cs sck si so msb high impedance instruction 16 bit address 15 14 13 3 2 1 0 figure 5. read eeprom array sequence x5168, x5169
9 fn8130.2 june 15, 2006 read sequence when reading from the eeprom memory array, cs is first pulled low to select the device. the 8-bit read instruction is transmitted to the device, followed by the 16-bit address. after the read opcode and address are sent, the data stored in the memory at the selected address is shifted out on the so line. the data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. the address is automatically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. the read operation is terminated by taking cs high. refer to the read eeprom array sequence (figure 1). to read the status register, the cs line is first pulled low to select the device followed by the 8-bit rdsr instruction. after the rdsr opcode is sent, the contents of the status register are shifted out on the so line. refer to the read status register sequence (figure 2). write sequence prior to any attempt to write data into the device, the ?write enable? latch (wel) must first be set by issuing the wren instruction (figure 3). cs is first taken low, then the wren instruction is clocked into the device. after all eight bits of the instruction are transmitted, cs must then be taken high. if the user continues the write operation without taking cs high after issuing the wren instruction, the write operation will be ignored. to write data to the eeprom memory array, the user then issues the write instruction followed by the 16 bit address and then the data to be written. any unused address bits are specified to be ?0?s?. the write operation minimally takes 32 clocks. cs must go low and remain low for the duration of the operation. if the address c ounter reaches the end of a page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that may have been previously written. for the page write operation (b yte or page write) to be completed, cs can only be brought high after bit 0 of the last data byte to be written is clocked in. if it is brought high at any other time, the write operation will not be completed (figure 4). to write to the status register, the wrsr instruction is followed by the data to be written (figure 5). data bits 0 and 1 must be ?0?. while the write is in progress following a status register or eeprom sequence, the status register may be read to check the wip bit. during this time the wip bit will be high. operational notes the device powers-up in the following state: ? the device is in the low power standby state. ? a high to low transition on cs is required to enter an active state and receive an instruction. ? so pin is high impedance. ? the write enable latch is reset. ? the flag bit is reset. ? reset signal is active for t purst . data protection the following circuitry has been included to prevent inadvertent writes: ? a wren instruction must be issued to set the write enable latch. ?cs must come high at the proper clock count in order to start a nonvolatile write cycle. x5168, x5169
10 fn8130.2 june 15, 2006 01234567891011121314 76543210 data out cs sck si so msb high impedance instruction figure 6. read status register sequence 01234567 cs si sck high impedance so figure 7. write enable latch sequence 32 33 34 35 36 37 38 39 sck si cs 012345678910 sck si instruction 16 bit address data byte 1 76543210 cs 40 41 42 43 44 45 46 47 data byte 2 76543210 data byte 3 76543210 data byte n 15 14 13 3 2 1 0 20 21 22 23 24 25 26 27 28 29 30 31 654 321 0 figure 8. write sequence x5168, x5169
11 fn8130.2 june 15, 2006 symbol table 0123456789 cs sck si so high impedance instruction data byte 765432 10 10 11 12 13 14 15 figure 9. status register write sequence waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance x5168, x5169
12 fn8130.2 june 15, 2006 absolute maximum ratings recommended operating conditions temperature under bias . . . . . . . . . . . . . . . . . . . . .-65c to +135c storage temperature . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage on any pin with respect to v ss . . . . . . . . . . . . -1.0v to +7v dc output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma lead temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300c temperature range commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c supply voltage limits -2.7 or -2.7a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v blank or -4.5a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v-5.5v caution: stresses above those listed under ?absolute maximum rating s? may cause permanent damage to the device. this is a stres s rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating conditions for extend ed periods may affect device reliability dc electrical specifications over the recommended operating condi tions unless otherwise specified. symbol parameter test conditions limits unit min typ max i cc1 v cc write current (active) sck = v cc x 0.1/v cc x 0.9 @ 2mhz, so = open 5ma i cc2 v cc read current (active) sck = v cc x 0.1/v cc x 0.9 @ 2mhz, so = open 0.4 ma i sb v cc standby current wdt = off cs = v cc , v in = v ss or v cc , v cc = 5.5v 1a i li input leakage current v in = v ss to v cc 0.1 10 a i lo output leakage current v out = v ss to v cc 0.1 10 a v il (note 1) input low voltage -0.5 v cc x 0.3 v v ih (note 1) input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage v cc > 3.3v, i ol = 2.1ma 0.4 v v ol2 output low voltage 2v < v cc 3.3v, i ol = 1ma 0.4 v v ol3 output low voltage v cc 2v, i ol = 0.5ma 0.4 v v oh1 output high voltage v cc > 3.3v, i oh = -1.0ma v cc - 0.8 v v oh2 output high voltage 2v < v cc 3.3v, i oh = -0.4ma v cc - 0.4 v v oh3 output high voltage v cc 2v, i oh = -0.25ma v cc - 0.2 v v ols reset output low voltage i ol = 1ma 0.4 v capacitance t a = +25c, f = 1mhz, v cc = 5v. symbol test conditions max. unit c out (note 2) output capacitance (so, reset /reset) v out = 0v 8 pf c in (note 2) input capacitance (sck, si, cs , wp )v in = 0v 6 pf notes: 1. v il min. and v ih max. are for reference only and are not tested. 2. this parameter is periodica lly sampled and not 100% tested. x5168, x5169
13 fn8130.2 june 15, 2006 equivalent a.c. load circuit at 5v v cc 5v output 100pf 5v 4.6k ? reset/reset 30pf 2.06k ? 3.03k ? a.c. test conditions input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 ac electrical specifications (over recommended operating conditions , unless otherwise specified.) symbol parameter 2.7-5.5v unit min max serial input timing f sck clock frequency 0 2 mhz t cyc cycle time 500 ns t lead cs lead time 250 ns t lag cs lag time 250 ns t wh clock high time 200 ns t wl clock low time 200 ns t su data setup time 50 ns t h data hold time 50 ns t ri (3) input rise time 100 ns t fi (3) input fall time 100 ns t cs cs deselect time 500 ns t wc (4) write cycle time 10 ms x5168, x5169
14 fn8130.2 june 15, 2006 serial input timing serial output timing notes: (3) this parameter is periodically sampled and not 100% tested. (4) t wc is the time from the rising edge of cs after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. serial output timing sck cs si so msb in t su t ri t lag t lead t h lsb in t cs t fi high impedance symbol parameter 2.7-5.5v unit min max f sck clock frequency 0 2 mhz t dis output disable time 250 ns t v output valid from clock low 200 ns t ho output hold time 0 ns t ro (3) output rise time 100 ns t fo (3) output fall time 100 ns sck cs so si msb out msb?1 out lsb out addr lsb in t cyc t v t ho t wl t wh t dis t lag x5168, x5169
15 fn8130.2 june 15, 2006 power-up and power-down timing reset output timing note: (5) this parameter is periodically sampled and not 100% tested. v trip set conditions v cc t purst t purst t r t f t rpd reset (x5168) 0 volts v trip v trip reset (x5169) symbol parameter min typ max unit v trip reset trip point voltage, x5168-4.5a, x5168-4.5a reset trip point voltage, x5168, x5169 reset trip point voltage, x5168-2.7a, x5169-2.7a reset trip point voltage, x5168-2.7, x5169-2.7 4.5 4.25 2.85 2.55 4.63 4.38 2.93 2.63 4.75 4.5 3.0 2.7 v v th v trip hysteresis (high to low vs. low to high v trip voltage) 20 mv t purst power-up reset time out 100 200 280 ms t rpd (5) v cc detect to reset/output 500 ns t f (5) v cc fall time 100 s t r (5) v cc rise time 100 s v rvalid reset valid v cc 1v sck si v p v p cs t vps t vph t p t vps t vph t rp t vpo t vpo t tsu t thd v trip v cc x5168, x5169
16 fn8130.2 june 15, 2006 v trip reset conditions sck si v cc v p cs t vps t vph t p t vps t vp1 t rp t vpo t vpo v cc * *v cc > programmed v trip v trip programming specifications v cc = 1.7-5.5v; temperature = 0c to 70c parameter description min max unit t vps sck v trip program voltage setup time 1 s t vph sck v trip program voltage hold time 1 s t p v trip program pulse width 1s t tsu v trip level setup time 10 s t thd v trip level hold (stable) time 10 ms t wc v trip write cycle time 10 ms t rp v trip program cycle recovery period (bet ween successive programming cycles) 10 ms t vpo sck v trip program voltage off time before next cycle 0 ms v p programming voltage 15 18 v v tran v trip programmed voltage range 1.7 5.0 v v ta1 initial v trip program voltage accuracy (v cc applied-v trip ) (programmed at 25c) -0.1 +0.4 v v ta2 subsequent v trip program voltage accuracy [(v cc applied-v ta1 )-v trip ] (programmed at 25c) -25 +25 mv v tr v trip program voltage repeatability (successive program operations) (programmed at 25c) -25 +25 mv v tv v trip program variation after programming (0-75c). (programmed at 25c) -25 +25 mv v trip programming parameters are periodically sampled and are not 100% tested. x5168, x5169
17 fn8130.2 june 15, 2006 typical performance 18 16 14 12 10 8 6 4 2 0 watchdog timer on (v cc = 5v) watchdog timer on (v cc = 5v) watchdog timer off (v cc = 3v, 5v) -40c 25c 90c temp (c) isb (a) v cc supply current vs. temperature (i sb ) v trip vs. temperature (programmed at 25c) t purst vs. temperature 5.025 5.000 4.975 3.525 3.500 3.475 2.525 2.500 2.475 025 85 voltage temperature v trip = 5v v trip = 3.5v v trip = 2.5v 200 195 190 185 180 175 170 165 160 -40 25 90 degrees c 205 time (ms) x5168, x5169
18 fn8130.2 june 15, 2006 x5168, x5169 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail ?x? c 0.010 mdp0027 small outline package family (so) symbol so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) tolerance notes a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. l 2/01 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994
19 fn8130.2 june 15, 2006 x5168, x5169 plastic dual-in-line packages (pdip) notes: 1. plastic or metal protrusions of 0.010? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions e and ea are measured with the l eads constrained perpendicular to the seating plane. 4. dimension eb is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. mdp0031 plastic dual-in-line package symbol pdip8 pdip14 pdip16 pdip18 pdip20 tolerance notes a 0.210 0.210 0.210 0.210 0.210 max a1 0.015 0.015 0.015 0.015 0.015 min a2 0.130 0.130 0.130 0.130 0.130 0.005 b 0.018 0.018 0.018 0.018 0.018 0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 d 0.375 0.750 0.750 0.890 1.020 0.010 1 e 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 e1 0.250 0.250 0.250 0.250 0.250 0.005 2 e 0.100 0.100 0.100 0.100 0.100 basic ea 0.300 0.300 0.300 0.300 0.300 basic eb 0.345 0.345 0.345 0.345 0.345 0.025 l 0.125 0.125 0.125 0.125 0.125 0.010 n 8 14 16 18 20 reference rev. b 2/99 d l a e b a1 note 5 a2 seating plane l n pin #1 index e1 12 n/2 b2 e eb ea c
20 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8130.2 june 15, 2006 x5168, x5169 thin shrink small outlin e plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ac, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m14.173 14 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.195 0.199 4.95 5.05 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n14 147 0 o 8 o 0 o 8 o - rev. 2 4/06

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